The present disclosure generally relates to a semiconductor switch, and particularly to a semiconductor switch circuit including a variable impedance single pole double throw (SPDT) switch.
A complementary metal oxide semiconductor (CMOS) switch can be employed to connect a semiconductor circuit to an antenna. The antenna can be employed to broadcast a signal that the semiconductor circuit generates, or can be employed to receive a signal to be relayed to the semiconductor circuit. Depending on whether the antenna broadcasts a signal or receives a signal, different signal paths are required between the antenna and the semiconductor circuit.
A single pole double throw (SPDT) switch is typically employed between the semiconductor circuit and the two signal paths to the antenna. A first path can include a series connection of a drive amplifier and a high power amplifier. To broadcast a signal, a signal generated by a section of the semiconductor circuit configured to encode the signal passes through the drive amplifier, the high power amplifier, and the SPDT switch, and subsequently reaches the antenna, which broadcasts the signal. The node between the SPDT switch and the high power amplifier is typically referred to as a transmitter node TX. A second path can include a series connection of a limiter and a low noise amplifier. To receive a signal, a signal captured by the antenna passes the SPDT switch, and then through the limiter and the low noise amplifier, arriving at a section the semiconductor circuit configured to decode the signal. The node between the SPDT switch and the limiter is typically referred to as a reception node RX.
Referring to FIG. 1, a prior art single pole double throw (SPDT) switch configured for use with an antenna includes a serial connection of a first transmission-side transistor MT1 and a reception-side transistor MR1 between a transmission node TX and a reception node RX. An antenna is connected to a node between the drains of the first transmission-side transistor MT1 and the reception-side transistor MR1. The gate and body of the first transmission-side transistor MT1 have fixed impedances, i.e., the resistance of a gate-side resistor Rg and the resistance of the body-side resistor Rw. Likewise, the gate and body of the first reception-side transistor MR1 have fixed impedances as well.
Typically, a second transmission-side transistor MT2 is provided between the transmission node TX and electrical ground. The body of the second transmission-side transistor MT2 is grounded through a body-side resistor Rw. Likewise, a second reception-side transistor MR2 is provided between the reception node RX and electrical ground. The body of the second reception-side transistor MR2 is grounded through a body-side resistor Rw.
The first transmission-side transistor MT1 and the first reception-side transistor MR1 operate complementarily, i.e., one is on and the other is off during normal operation. Likewise, the second transmission-side transistor MT2 and the second reception-side transistor MR2 operate complementarily. During a transmission mode, the first transmission-side transistor MT1 and the second reception-side transistor MR2 are turned on, and the first reception-side transistor MR1 and the second transmission-side transistor MT2 are turned off. A signal path from the transmission node TX to the antenna is connected during the transmission mode, while the first reception-side transistor MR1 provides electrical isolation between the antenna and the reception node RX. During a reception mode, the first transmission-side transistor MT1 and the second reception-side transistor MR2 are turned off, and the first reception-side transistor MR1 and the second transmission-side transistor MT2 are turned on. A signal path from the reception node RX to the antenna is connected during the reception mode, while the first transmission-side transistor MT1 provides electrical isolation between the antenna and the transmission node TX.
The SPDT switch needs to transmit a signal through one path, while decoupling the signal in the other path in order to provide a high fidelity signal, i.e., a signal with a high signal-to-noise ratio. In order to broadcast a signal with high fidelity, an SPDT switch needs to minimize signal loss connecting to the transmitter node TX to pass signal to the antenna, while suppressing and electrically isolating the reception node RX. In order to preserve the fidelity of the signal received from the antenna, an SPDT switch needs to minimize signal loss connecting to the reception node RX to receiver the signal from the antenna, while suppressing and electrically isolating the transmitter node TX. The signal loss in a signal path due to the presence of the first transmission-side transistor MT1 or the first reception-side transistor MR1 is referred to as insertion loss. Ideally, the insertion loss should be zero decibel. The attenuation of the electrically isolated signal across the source and the drain of a turned-off first transistor, i.e., either the first transmission-side transistor MT1 or the first reception-side transistor MR1 in a turned-off state, is referred to as noise isolation. Ideally, the noise isolation should be a large negative number in decibels. An ideal SPDT switch thus needs to provide low signal loss and effective noise isolation at the same time. In the prior art SPDT switch of FIG. 1, the fixed impedance values within the circuit place a limit on the insertion loss and noise isolation.